Digital Hardware AI Architectures

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DESCRIPTION

The Digital Hardware AI Architecture chair focuses on the integration of highly energy efficient hardware/software architectures to implement AI tasks in general, and deep neural networks in particular.

The main challenges address the tight integration of AI accelerators in software-intensive systems bearing in mind a wealth of non-functional requirements: low to very low power consumption, easy system-level co-processor usage, results reproducibility, real-time and low latency computations, AI functions virtualization for deployment on diverse execution platforms, compatibility with academic or industrial machine learning frameworks, etc.

ACTIVITIES

Cooperation between University of Salerno, Italy, STMicroelectronics, Agrate, IT, and the Chair to work on tiny binary neural netwoks.
A Cifre PhD has started in cooperation with STMicroelectronics, Crolles, on an ultra-low power TPU.
The idea of a TCAM based ternary neural network accelerator is under investigation, to build an high-efficiency very low power matrix multiplication engine.
Compression of table based implementation of complex functions (exponentiation, logarithms, trigonometric, etc) for FPGA is being studied as a solution to maximize FPGA usage for convolution and activation functions computation.
Finally, an FPGA backend for Pytorch is being elaborated, to ease the hardware design exploration of network architectures.

CHAIR EVENTS

Invited speech at the Applied Machine Learning Days, in Lausanne, Swiss, January 25-29, 2020.

SELECTED LIST OF PUBLICATIONS 

  • Liliana Lilibeth Andrade Porras, Thomas Baumela, Frédéric Pétrot, D. Briand, Olivier Bichler et al. Efficient deep learning approach for fault detection in the semiconductor industry. ADTC 2021 - European Nanoelectronics Applications Design & Technology Conference, Jun 2021, Grenoble, France.

  • Tiago Trevisan Jost, Yves Durand, Christian Fabre, Albert Cohen, Frédéric Pétrot. Seamless Compiler Integration of Variable Precision Floating-Point Arithmetic. International Symposium on Code Generation and Optimization (CGO 2021), Feb 2021, Atlanta, United States.

  • M. Badaroux, Saverio Miroddi, Frédéric Pétrot. To Pin or Not to Pin: Asserting the Scalability of QEMU Parallel Implementation. 24th Euromicro Conference on Digital System Design (Euromicro DSD/SEAA 2021), Sep 2021, Palermo, Italy. pp.238-245.

  • M. Badaroux, Frédéric Pétrot. Arbitrary and Variable Precision Floating-Point Arithmetic Support in Dynamic Binary Translation. 26th Asia and South Pacific Design Automation Conference (ASP-DAC 2021), Jan 2021, Tokyo (Virtual event), Japan.

  • B.J. Fernandez-Mesa, Liliana Lilibeth Andrade Porras, Frédéric Pétrot. Simulation of Ideally Switched Circuits in SystemC. Asia and South Pacific Design Automation Conference (ASP-DAC 2021), Jan 2021, Tokyo, Japan.

  • B.J. Fernandez-Mesa, Liliana Lilibeth Andrade Porras, Frédéric Pétrot. Synchronization of Continuous Time and Discrete Events Simulation in SystemC. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2021, 40 (7), pp.1450 – 1463.

  • L. Bonicel, R. Bohrer, B. Leprettre, Frédéric Pétrot, Frédéric Rousseau. Component Based Framework for Designing and Validating Asynchronous Algorithms for Electrical Measurement and Protection. 4th IEEE International Conference on Industrial Cyber-Physical Systems (ICPS 2021), May 2021, Victoria, BC, Canada.

  • Jean Bruant, Pierre-Henri Horrein, Olivier Muller, Tristan Groleat, Frédéric Pétrot. Towards Agile Hardware Designs with Chisel: a Network Use-case. IEEE Design & Test, IEEE, 2021.

  • Low Power Tiny Binary Neural Network with improved accuracy in Human Recognition Systems. Euromicro Conference DSD, August 26 – 28, 2020.
Published on  January 9, 2024
Updated on January 9, 2024