Hardware for spike-coded neural networks exploiting hybrid CMOS non-volatile technologies

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DESCRIPTION

The grand challenge of this Chair of Excellence is to enable the arrival of the third generation of Neural Networks, namely Spiking ones (SNN).

SNNs get inspiration from biological system, whose computations are 3 to 6 orders of magnitude more energy efficient than current dedicated digital neural network implementations. The objective is to bridge the gap thanks to massively parallel, configurable non von-Neumann spike-based architectures, based on very dense intertwined computation and storage elements, harnessing self-learning and self-organizing capabilities.

This chair builds upon a multidisciplinary team, necessary to strike the right combination of learning algorithms, large-scale power efficient accelerators and industrial applications.

ACTIVITIES

The Chair has hired two PhD students, for working on the coding and learning strategies on one side, and on the architecture definition and circuit design on the other side. This software-hardware co-design approach is key for obtaining large energy efficiency gains.

Work is currently ongoing on specifying, among all the possible AI applications, which ones will benefit the most from spike coding.

CHAIR EVENTS

A. Valentian, “Choosing the right combination of technology, design and tools is key for successful Edge AI solutions,” Keynote Talk, ValleyML AI Expo 2020 Conference Series, Virtual event, October 2020

F. Petrot, L. Anghel, L. Andrade, “State of the Art I Hardware-accelerated neural networks”, Inited Presentation, Applied Machine ELarning days @ EFFL, 27 January 2020

SELECTED LIST OF PUBLICATIONS

  • L. Anghel, Binarized Ensemble Neural Networks based on spintronic devices- november 2021,IEEE / ACM International Symposium on Nanoscale Architectures.

  • A. Valentian, “Les approches hardware de l'IA économe en énergie,” Présentation invitée, Planet Tech’Care, Atelier - IA et consommation énergétique, Février 2021.

  • A. Valentian, W. Weinreich, “AI chips for the edge – New computing architectures for low-power AI,” EU Japan Symposium on semiconductors, Virtual event, April 2021.

  • A. Valentian, “How to design a power frugal hardware for AI – The bio-inspiration path,” Tiny ML Talks, Webcast, September 2021.

  • V. Cinçon, Elena Ioana Vatajelu, Lorena Anghel, Philippe Galy, “From 1.8V to 0.19V voltage bias on analog spiking neuron in 28nm UTBB FD-SOI technology”, IEEE conference EUROSOI-ULIS, september 2020

  • A. Valentian, “Choosing the right combination of technology, design and tools is key for successful Edge AI solutions,” Keynote Talk, ValleyML AI Expo 2020 Conference Series, October 2020.

  • A. Valentian, F. Rummens, E. Vianello, T. Mesquida, C. Lecat-Mathieu de Boissac, O. Bichler, C. Reita, “Fully Integrated Spiking Neural Network with Analog Neurons and RRAM Synapses,” IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, December 2019.

  • M. Bouvier, A. Valentian, T. Mesquida, F. Rummens, M. Reyboz, E. Vianello, E. Beigné, “Spiking Neural Networks Hardware Implementations and Challenges: a Survey,” ACM Journal on Emerging Technologies in Computing Systems (ACM JETC), Special Issue on Hardware and Algorithms for Energy-Constrained On-chip Machine Learning, August 2019
Published on  January 9, 2024
Updated on January 9, 2024